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1987-01-02
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L O G S I M
a Logic Simulation program
Version 2.1
Copyright (C), 1986 by Scott Romanowski
All rights reserved
Commercial Duplication Prohibited
November 20, 1986
I
Contents
1. Introduction........................................... 1
1.1 Duplication and Use Policy.......................... 1
2. Using LOGSIM........................................... 2
2.1 Equation Syntax and Node Numbers.................... 3
2.2 Tri-State and Open Collector Outputs................ 3
2.3 Initial Conditions.................................. 4
3. Describing the Circuit................................. 4
3.1 Gates............................................... 4
3.1.1 AND Gate........................................ 5
3.1.2 BUFFER Gate..................................... 5
3.1.3 DELAY Gate...................................... 5
3.1.4 DELAYH Gate..................................... 6
3.1.5 DELAYL Gate..................................... 6
3.1.6 NAND Gate....................................... 6
3.1.7 NOR Gate........................................ 6
3.1.8 NOT Gate........................................ 7
3.1.9 OR Gate......................................... 7
3.1.10 XNOR Gate...................................... 7
3.1.11 XOR Gate....................................... 7
3.2 Chips............................................... 8
3.2.1 D Chip Descriptor............................... 8
3.2.2 JK Chip Descriptor.............................. 8
3.2.3 7476 Chip Descriptor............................ 9
3.2.4 74112 Chip Descriptor........................... 9
3.2.5 74123 Chip Descriptor........................... 9
3.2.6 74126 Chip Descriptor.......................... 10
3.2.7 74192 Chip Descriptor.......................... 10
3.2.8 74193 Chip Descriptor.......................... 10
3.2.9 74253 Chip Descriptor.......................... 11
3.3 Clocks............................................. 11
3.4 Data Sources....................................... 11
4. Simulating the Circuit................................ 12
4.1 Simulation Time.................................... 12
4.2 Rise Time Calculations............................. 12
4.3 Gate Delays........................................ 13
4.4 Initial Conditions................................. 13
4.5 Output Modes....................................... 14
4.5.1 Display........................................ 14
4.5.2 File........................................... 14
4.5.3 Print.......................................... 15
4.5.4 Fprint......................................... 16
4.6 Time Units per Screen.............................. 17
4.7 Monitoring nodes................................... 17
4.8 Fanout Lists....................................... 17
5. Chip Descriptions..................................... 17
5.1 Making New Chips................................... 18
5.1.1 Pins, Delay, Mode and Output Pins.............. 18
5.1.2 Chip Modes..................................... 19
5.1.3 Output Equations............................... 19
5.2 Sample Chip Descriptions........................... 20
5.3 Simulating ROMS.................................... 20
5.4 Simulating RAMS.................................... 21
LOGSIM
II
5.5 Simulating PALs and PLAs........................... 21
LOGSIM
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1. Introduction
LOGSIM is a digital logic simulation program. It is
very general and infinitely expandable. Users create a file
describing their circuit and select options to configure the
simulation.
All times in the circuit are measured in "time units".
A time unit is any amount of time, determined by the user.
If the user wants to use 10 nanoseconds per time unit, then
a 100 nanosecond delay would be 10 time units.
Logic values are simply represented as high and low
states, the actual voltage levels are immaterial to LOGSIM.
Tri-state and open collector outputs are handled specially--
see the section describing them below.
LOGSIM requires DOS 2.1 or higher and one disk drive.
To use the PRINT option (graphics timing diagram on the
printer), the graphics screen dump program included in DOS
is required. Using PC-DOS, this program is called
GRAPHICS.COM, using MS-DOS, this program is one of the
PSCxxxx.COM programs. See your DOS manual for more informa-
tion.
This manual is written for people who have some famil-
iarity with DOS (somewhere between neophyte and wizard).
You must be able to edit files to use LOGSIM. Knowledge of
the print screen command, file and path names, default
drive, default directory, and batch files will help, but is
not required. It goes without saying, but you must know
about digital logic before understanding what this program
does.
1.1 Duplication and Use Policy
LOGSIM is distributed as shareware. You can make as
many copies as you desire, and give away as many copies as
desired. Users may not charge others for copies of this
program without the express written permission of the au-
thor. If you must charge for the disk(s) when you give away
a copy, you may charge no more than $1.00 (one dollar) per
disk.
If you distribute this program, you must include this
policy with the copy. You may not include any portion of
this program, modified or not, in any other program without
the written permission of the author.
If you are pleased with this program, the author humbly
requests that you send $20 to the author. Shareware is
LOGSIM
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based on the belief that people will gladly pay for a good
product, yet should not be required to pay for a bad prod-
uct. Shareware lets people experiment with programs, and
form their own opinion of the product.
If you choose not to support the author, there is noth-
ing to stop you from continuing to use LOGSIM. If you sup-
port the author, good for you! You have made the author
very happy.
The author can be reached at:
Scott Romanowski
5 Sherburn Place
Wilmington, MA 01887
In addition, improvements to LOGSIM are planned. These
improvements will speed simulation, allow larger circuits,
allow easy implementation of RAM memories, and add more
standard chips. If this program generates a good response,
the author will surely distribute the updates. On the other
hand, a discouraged author probably won't.
2. Using LOGSIM
In order to have LOGSIM simulate your circuit, you must
create a circuit descriptor file describing your circuit.
To use LOGSIM, at the DOS prompt, type "LOGSIM". LOGSIM
will reply with "Circuit Descriptor file", to which you type
the name of the circuit descriptor file. Optionally, you
can include the name of the circuit descriptor file on the
command line, by typing "LOGSIM filename" (where filename is
the name of the circuit descriptor file).
A circuit descriptor file consists of two parts: the
circuit itself, and a list of options for LOGSIM. The two
parts are separated by an END statement--simply a line with
the word END.
A sample circuit descriptor is shown below:
JK H 14 1 H 2 13 3
JK H 15 1 H 2 14 4
JK H 5 1 H 2 15 16
AND 5 3 4
CLOCK 1 0000111
DATA 2 01
END
TIME 60
MONITOR 13 14 15
PRINT
The first 6 lines describe the circuit (in this case a
simple 0-1-2-4 counter), the 7th line is the end statement,
LOGSIM
3
and lines 8 through 10 are the options. LOGSIM recognizes
both upper and lower case letters, and both can be freely
mixed in your input.
When LOGSIM is reading your circuit description, it
displays "Reading element ..." messages to inform you of its
progress, and to aid in debugging if there is an error in
your circuit description. After LOGSIM is finished reading
your circuit descriptor, LOGSIM prints "Circuit descriptor
read in" and starts simulating your circuit. There may be a
few second pause while LOGSIM determines the initial state
of the circuit.
2.1 Equation Syntax and Node Numbers
Logical expressions are only used in coding chip de-
scriptors. In that case and in this manual, LOGSIM uses the
following symbols when representing logic equations:
~ NOT & AND + OR * XOR
These are listed in order of precedence, except OR and
XOR are the same precedence. Expressions are evaluated from
left to right. Parentheses (parentheses only, no brackets
[] or braces {} ) can be used to group expressions and over-
ride precedence. This precedence scheme can be best shown
by some examples:
A & B + C = C + A & B = (A & B) + C
A + B * C = (A + B) * C
A * B + C = (A * B) + C
~A & B & ~C = ( (~A) & B) & (~C)
~(A + B) & ~C + D = ( ( ~(A + B) ) & (~C) ) + D
All nodes in LOGSIM are numbered. Any integer from 0
to 1,000 can be used. In addition, there are two special
nodes: H (a constant logic high) and L (a constant logic
low), which can be used chip input nodes. Example: JK h 2 3
4 5 6 7 is a JK flip flop with ~PRESET tied to logic high.
Using the nodes H or L in a gate (ex.: AND 4 H 3) is WRONG!
and will cause errors!
There can be up to one thousand nodes in a circuit
descriptor.
2.2 Tri-State and Open Collector Outputs
In LOGSIM, all outputs are capable of being wired-ANDed
together (like open-collector outputs). If you connect sev-
eral outputs together, the state at that node will be a
logic high if and only if all the outputs on that node are
LOGSIM
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logic highs. If any output to that node is a logic low, the
node will be a logic low.
Tri-state devices are implemented by having the output
of the device go high in the high-Z state. For example,
consider a tri-state inverter with the following truth
table:
A B C (Output)
L X Z (high impedance)
H L H
H H L
In LOGSIM, this can be represented by the equation
C = ~A + B. Note that in LOGSIM, and this manual, the "~"
is used to show negation, "~A" means "NOT A".
2.3 Initial Conditions
Before LOGSIM starts simulating your circuit, it must
determine the initial state of your circuit. To do this it
assumes that all nodes start at high logic states, holds
clocks and data sources in their initial states, and repeat-
edly calculates new states for your circuit. During this
process, all delays in the circuit are set to one time unit.
You are responsible for ensuring that the circuit
starts in a known state! The easiest way is to have a data
source that initializes the circuit elements as necessary,
and then goes to an inactive state after one time unit. If
the circuit contains unstable elements, LOGSIM will inform
you of that fact with a message "Element driving node xx is
unstable."
The INITIAL option (see below) can be used to manually
set the state of your circuit. If this is done, LOGSIM uses
that as the initial state and does not use this process.
3. Describing the Circuit
The circuit description consists of a number of lines,
each of which is an element, followed by an END line. Each
line is either a gate, chip, clock, or data source.
Very Important! Use only spaces to separate items. Do
not use commas, or any other punctuation.
3.1 Gates
LOGSIM has some standard gates--AND, NAND, OR, NOR,
XOR, XNOR, NOT, BUFFER, DELAYH, DELAYL, and DELAY--built in.
LOGSIM
5
All the gates have one output node, and the AND, NAND, OR,
NOR, XOR and XNOR can take up to 32 input nodes. The NOT
gate is a simple inverter, the BUFFER gate is a non-invert-
ing buffer, and the DELAY gate is a non-inverting buffer
with a constant, specified delay. The DELAYH and DELAYL
gates are similar to the DELAY gate, except that they only
delay high or low logic states (respectively) by the con-
stant delay. The opposite state (low for a DELAYH, high for
a DELAYL) is delayed by only 1 time unit. These gates are
further described below, and the default gate delay (1 time
unit + 1 time unit per input driven) formula can be changed
by the GATEDELAY option described below.
3.1.1 AND Gate
Syntax: AND [output] [input] [input] [input] ...
This gate ANDs together all the input nodes and outputs
that value to the output node. Up to 32 nodes can be ANDed
together with one gate. This gate has a default delay of 1
time unit + 1 time unit per input driven.
Example: AND 3 1 2 5 15 will generate a high at node 3
if all of nodes 1, 2, 5, and 15 are high.
3.1.2 BUFFER Gate
Syntax: BUFFER [output] [input]
This gate is a non-inverting buffer--the value of the
input appears at the output. This gate only takes one input,
and has a default delay of 1 time unit + 1 time unit per in-
put driven.
Example: BUFFER 4 5. Node 4 equals the value of node 5
(after the gate's inherent delay of course).
3.1.3 DELAY Gate
Syntax: DELAY [output] [input] [delay]
This gate is a non-inverting buffer with a constant de-
lay. Use this to simulate any fixed delay in the circuit.
This gate only takes one input. The longest delay possible
in LOGSIM is 32,767 time units.
Example: DELAY 12 1 10. The value of node 1 will ap-
pear at node 12 after a delay of 10 time units.
LOGSIM
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3.1.4 DELAYH Gate
Syntax: DELAYH [output] [input] [delay]
This gate is a non-inverting buffer which delays logic
high states by a constant delay. The longest delay possible
in LOGSIM is 32,767 time units. This gate only takes one
input. For example, if the input to a DELAYH gate (with a 4
time unit delay) is the pattern:
000011111111100000001000000, the output will be
000000001111110000000000000.
Example: DELAYH 12 1 10. The value of node 1 will ap-
pear at node 12 after a delay of 10 time units if it is a
logic high, or 1 time unit if it is a logic low.
3.1.5 DELAYL Gate
Syntax: DELAYL [output] [input] [delay]
This gate is a non-inverting buffer which delays logic
low states by a constant delay. The longest delay possible
in LOGSIM is 32,767 time units. This gate only takes one
input. For example, if the input to a DELAYL gate (with a 4
time unit delay) is the pattern:
111100000000011111110111111, the output will be
111111110000001111111111111.
Example: DELAYL 12 1 10. The value of node 1 will ap-
pear at node 12 after a delay of 10 time units if it is a
logic low, or 1 time unit if it is a logic high.
3.1.6 NAND Gate
Syntax: NAND [output] [input] [input] [input] ...
This gate NANDs together all the input nodes and out-
puts that value to the output node. Up to 32 nodes can be
NANDed together with one gate. This gate has a default de-
lay of 1 time unit + 1 time unit per input driven.
Example: NAND 3 1 2 5 15 will generate a low at node 3
if all of nodes 1, 2, 5, and 15 are high.
3.1.7 NOR Gate
Syntax: NOR [output] [input] [input] [input] ...
This gate NORs together all the input nodes and outputs
that value to the output node. Up to 32 nodes can be NORed
LOGSIM
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together with one gate. This gate has a default delay of 1
time unit + 1 time unit per input driven.
Example: NOR 3 1 2 5 15 will generate a low at node 3
if any of nodes 1, 2, 5, or 15 is high.
3.1.8 NOT Gate
Syntax: NOT [output] [input]
This gate is simple inverter--the value of the input is
inverted and appears at the output. This gate only takes one
input, and has a default delay of 1 time unit + 1 time unit
per input driven.
Example: NOT 4 5. Node 4 equals the inverse of the
value of node 5 (after the gate's inherent delay of course).
3.1.9 OR Gate
Syntax: OR [output] [input] [input] [input] ...
This gate ORs together all the input nodes and outputs
that value to the output node. Up to 32 nodes can be ORed
together with one gate. This gate has a default delay of 1
time unit + 1 time unit per input driven.
Example: OR 3 1 2 5 15 will generate a high at node 3
if any of nodes 1, 2, 5, or 15 is high.
3.1.10 XNOR Gate
Syntax: XNOR [output] [input] [input] [input] ...
This gate XNORs together all the input nodes and out-
puts that value to the output node. Up to 32 nodes can be
XNORed together with one gate. This gate has a default de-
lay of 1 time unit + 1 time unit per input driven.
Example: XNOR 3 1 2 5 15 will generate a high at node 3
if the value of node 3 exclusive-or the value of node 2 ex-
clusive-or the value of node 5 exclusive-or the value of
node 15 is a logic low.
3.1.11 XOR Gate
Syntax: XOR [output] [input] [input] [input] ...
This gate XORs together all the input nodes and outputs
that value to the output node. Up to 32 nodes can be XORed
LOGSIM
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together with one gate. This gate has a default delay of 1
time unit + 1 time unit per input driven.
Example: XOR 3 1 2 5 15 will generate a high at node 3
if the value of node 3 exclusive-or the value of node 2 ex-
clusive-or the value of node 5 exclusive-or the value of
node 15 is a logic high.
3.2 Chips
Syntax: [chip name] [pin assignments]
LOGSIM provides a facility for adding new circuit ele-
ments--chip descriptors. A chip descriptor is a file that
describes the function a chip. It can also be used as a
macro facility to simulate large chunks of circuitry. If
LOGSIM does not recognize an element as a gate, it searches
for a file with the same name. You can provide full DOS
paths as your chip name. For example, if your chip is
called "JK" in your circuit descriptor file, LOGSIM looks in
the current directory of the current drive for a file named
JK. If you called it "B:\logsim\chips\jk.dat", LOGSIM would
search for the file B:\LOGSIM\CHIPS\JK.DAT.
After the name, the pin assignments are listed. This
is a of what node each pin is tied to, starting with pin 1.
If you had a four pin chip named "4PIN" and pin 1 was tied
to node 4, pin 2 to node 3, pin 3 to a constant high and pin
4 to node 2, the line in the circuit descriptor would be:
4PIN 4 3 h 2
A chip can have up to sixty pins.
Several standard chips are included in LOGSIM, all are
standard DIP packages. They are described below:
3.2.1 D Chip Descriptor
The D chip descriptor is identical to the 7476 chip de-
scriptor (see below). It is included only for compatibility
with LOGSIM version 1.0.
3.2.2 JK Chip Descriptor
The JK chip descriptor is identical to the 74112 chip
descriptor (see below). It is included only for compatibil-
ity with LOGSIM version 1.0.
LOGSIM
9
3.2.3 7476 Chip Descriptor
The 7476 Chip Descriptor represents ½ of a 7476 chip, and is
a negative-edge triggered D flip flop with active-low preset
and clear. The pin assignment is: (1) ~Preset; (2) D; (3)
Clock; (4) ~Clear; (5) Q; (6) ~Q
Function Table
Inputs Outputs
~PRE ~CLR CLK D | Q ~Q